doi:
UDK: 621.314.5

THE EFFECT OF TRANSISTOR SWITCHING TIME AND PARASITIC CIRCUIT PARAMETERS ON THE LEVEL OF INTERFERENCE GENERATED BY THE INVERTER

Воршевский А. А., Воршевский П. А., Гургенян Г. Г.
Article language: английский

Annotation

The mechanism of interference during operation of the inverter is considered. The necessity of taking into account the parasitic parameters of the elements when calculating the interference is evaluated. The circuit for modeling of pulse voltage generation in nanosecond scale is presented. The results of voltage modeling give the information about influence of the switching time of transistors and parasitic parameters of components on noise amplitude. Keywords: electromagnetic interference, inverter, parasitic parameters, switching time, electromagnetic compatibility

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